CD74FCT651

Features: • Buffered Inputs• Typical Propagation Delay: 6.8ns at VCC = 5V, TA = 25, CL = 50pF• CD75FCT651 - Inverting• CD74FCT652 - Noninverting• Family Features - SCR Latchup Resistant BiCMOS Process and Circuit Design - Speed of Bipolar FAST™/AS/S - 64mA Outpu...

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SeekIC No. : 004311942 Detail

CD74FCT651: Features: • Buffered Inputs• Typical Propagation Delay: 6.8ns at VCC = 5V, TA = 25, CL = 50pF• CD75FCT651 - Inverting• CD74FCT652 - Noninverting• Family Features - SCR ...

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Part Number:
CD74FCT651
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/10/30

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Product Details

Description



Features:

• Buffered Inputs
• Typical Propagation Delay: 6.8ns at VCC = 5V, TA = 25, CL = 50pF
• CD75FCT651
   - Inverting
• CD74FCT652
   - Noninverting
• Family Features
   - SCR Latchup Resistant BiCMOS Process and Circuit Design
   - Speed of Bipolar FAST™/AS/S
   - 64mA Output Sink Current
   - Output Voltage Swing Limited to 3.7V at VCC = 5V
   - Controlled Output Edge Rates
   - Input/Output Isolation to VCC
   - BiCMOS Technology with Low Quiescent Power



Pinout

  Connection Diagram


Specifications

DC Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK (For VI < -0.5V) . . . . . . . . .  . . -20mA
DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . .  . -50mA
DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . .70mA
DC Output Source Current per Output Pin, IO . . . . . . . . . . . -30mA
DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140mA
DC Ground Current (IGND). . . . . . . . . . . . . . . . . . . . . . . . . . .528mA



Description

The CD74FCT651 and CD74FCT652 three-state, octal bus transceivers/registers use a small geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output HIGH level to two diode drops below VCC. This resultant lowering of output swing (0V to 3.7V) reduces power bus ringing (a source of EMI) and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 64 milliamperes.

CD74FCT651 consist of bus transceiver circuits, D-Type flipflops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. CD74FCT651 Output Enables OEAB and OEBA are provided to control the transceiver functions. SAB and SBA control pins are provided to select whether real-time or stored data is transferred. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A CD74FCT651 LOW input level selects real-time data and a HIGH selects stored data. The following examples demonstrate the four fundamental bus management functions that can be performed with the octal bus transceivers and registers.

Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low to high transitions at the appropriate clock pins (CAB or CBA) regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, CD74FCT651 is also possible to store data without using the internal D-Type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state.




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