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CD74ACT153

Features: Buffered InputsTypical Propagation Delay - 6.3ns at VCC = 5V, TA = 25oC, CL = 50pFExceeds 2kV ESD Protection MIL-STD-883, Method 3015SCR-Latchup-Resistant CMOS Process and Circuit DesignSpeed of Bipolar FAST™/AS/S with Significantly Reduced Power ConsumptionBalanced Propagation Del...

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SeekIC No. : 004311905 Detail

CD74ACT153: Features: Buffered InputsTypical Propagation Delay - 6.3ns at VCC = 5V, TA = 25oC, CL = 50pFExceeds 2kV ESD Protection MIL-STD-883, Method 3015SCR-Latchup-Resistant CMOS Process and Circuit DesignSp...

CD74ACT153 Data Sheet

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Part Number:
CD74ACT153
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

Buffered Inputs
Typical Propagation Delay - 6.3ns at VCC = 5V, TA = 25oC, CL = 50pF
Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
SCR-Latchup-Resistant CMOS Process and Circuit Design
Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
Balanced Propagation Delays
AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50W Transmission Lines


Pinout

Connection Diagram




Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . .  . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA


Description

The CD74AC153 and CD74ACT153 are dual 4-input multiplexers that utilize the Harris Advanced CMOS Logic technology.
One of the four sources for each section is selected by the common Select inputs, S0 and S1. When the Enable inputs (1E, 2E) are HIGH, the outputs are in the low state.


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