CD74AC74

Features:

Buffered Inputs
Typical Propagation Delay (AC00) - 4.9ns at VCC = 5V, TA = 25^oC, CL = 50pF
Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
SCR-Lachup-Resistant CMOS Process and Circuit Design
Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
Balanced Propagation Delays
AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50W Transmission Lines


Pinout




Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 6) . . . . . . . . .±100mA


Description

The Harris CD74AC74 and CD74ACT74 dual D-type, positiveedge triggered flip-flops use the Harris ADVANCED CMOS technology. These flip-flops have independent DATA, SET, RESET, and CLOCK inputs and Q and Q outputs. The CD74AC74 logic level present at the data input is transferred to the output during the positive going transition of the clock pulse.
SET and RESET are independent of the clock and are accomplished by a low level at the appropriate input.