CD74AC174

Features:

Buffered Inputs
Typical Propagation Delay - 6.4ns at VCC = 5V, TA = 25oC, CL = 50pF
Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
SCR-Latchup-Resistant CMOS Process and Circuit Design
Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
Balanced Propagation Delays
AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50W Transmission Lines

Pinout




Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA


Description

The CD74AC174 and 'ACT174 are hex D flip-flops with reset that utilize Advanced CMOS Logic technology. Information at the D input is transferred to the Q output on the positivegoing edge of the clock pulse. All six flip-flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock.