Features: SpecificationsDescription The CD54/74HC192 has the following features including Synchronous Counting and Asynchronous Loading;Two Outputs for N-Bit Cascading; Look-Ahead Carry for High-Speed Counting;Fanout (Over Temperature Range), Standard Outputs--10 LSTTL Loads,Bus Driver Outputs --1...
CD54/74HC192: Features: SpecificationsDescription The CD54/74HC192 has the following features including Synchronous Counting and Asynchronous Loading;Two Outputs for N-Bit Cascading; Look-Ahead Carry for High-Spe...
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Features: • 'HC161, 'HCT161 4-Bit Binary Counter, Asynchronous Reset• 'HC163, 'HCT163 ...
Features: • 'HC161, 'HCT161 4-Bit Binary Counter, Asynchronous Reset• 'HC163, 'HCT163 ...
The CD54/74HC192 has the following features including Synchronous Counting and Asynchronous Loading;Two Outputs for N-Bit Cascading; Look-Ahead Carry for High-Speed Counting;Fanout (Over Temperature Range), Standard Outputs--10 LSTTL Loads,Bus Driver Outputs --15 LSTTL Loads;Wide Operating Temperature Range -- -55oC to 125oC;Balanced Propagation Delay and Transition Times;Significant Power Reduction Compared to LSTTL Logic ICs; HC Types.
The 'HC192, 'HC193 and 'HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL). The CD54/74HC192 counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock- Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). CD54/74HC192 high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The CD54/74HC192 Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and Clock-Down inputs, respectively, of the next most significant counter.If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, CD54/74HC192 will return to the normal sequence in one count as shown in state diagram.
The CD54/74HC192 information provided on this page represents TI's knowledge and belief as of the date that CD54/74HC192 is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such CD54/74HC192 information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.