Features: * Hysteresis on Clock Inputs for Improved Noiseimmunity and Increased Input Rise and Fall Times* Asynchronous Set and Reset* Complementary Outputs* Buffered Inputs* Typical fMAX = 50MHz at V = 5VL, CCC = 15pF, TA = 25* Fanout (Over Temperature Range)- Standard Outputs. . . . . . . . . . ...
CD54HCT74: Features: * Hysteresis on Clock Inputs for Improved Noiseimmunity and Increased Input Rise and Fall Times* Asynchronous Set and Reset* Complementary Outputs* Buffered Inputs* Typical fMAX = 50MHz at...
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Features: • 'HC161, 'HCT161 4-Bit Binary Counter, Asynchronous Reset• 'HC163, 'HCT163 ...
Features: • 'HC161, 'HCT161 4-Bit Binary Counter, Asynchronous Reset• 'HC163, 'HCT163 ...
The 'HC74 and 'HCT74 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts.They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
This flip-flop has independent DATA, SET, RESET and CLOCK inputs and Q and Q outputs. The CD54HCT74 logic level present at the data input is ransferred to the output during the positive-going transition of the clock pulse. SET and RESET are independent of the clock and are accomplished by a low evel at the appropriate input.
The HCT logic family is functionally as well as pin compatible with the standard LS logic family.