CD54HCT390

The CD74HC390 and'HCT390 dual 4-bitdecade ripple counters are high-speed silicon-gate CMOS devices and are pin compatible with low-power Schottky TTL (LSTTL).CD54HCT390 are divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide- by-5sections.The sesections are no rmallyused in a BCD decader bi-quinary configuration,since they share acommon master reset (nMR) .If the two master reset inputs(1MR and 2MR) are used to simulta neously clear all 8 bits of the counter,an umber of counting configurations are possible within one package.The separate clock in puts(n CP0  and nCP1 ) of each section allow ripple counter or frequency division applications of divide-by-2,4.5,10,20,25,50or100. Each section is triggered by the High-to-Low transition of the input pulses (n CP0  and n CP1 ).

For BCD decade operation,then Q0 out put is connected to thenCP1  input of the divide-by-5section.Forbi-quinary decade operation,then O3 output is connected to ThenCP0  input and nQ 0 becomes the decade output.

The CD54HCT390 master reset inputs (1MRand2MR) are active-High asynch ronousin puts to each decade counter whichoper-ate sonthe portion of the counte riden tified by the"1"and"2"prefixes in the pin configuration. A CD54HCT390 High level on then MR input overrides the clock and sets the four outputs Low.