Features: • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times• Asynchronous Reset• Complementary Outputs• Buffered Inputs• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25 • Fanout (Over Temperature Range) - Stand...
CD54HCT107: Features: • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times• Asynchronous Reset• Complementary Outputs• Buffered Inputs• ...
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Features: • 'HC161, 'HCT161 4-Bit Binary Counter, Asynchronous Reset• 'HC163, 'HCT163 ...
Features: • 'HC161, 'HCT161 4-Bit Binary Counter, Asynchronous Reset• 'HC163, 'HCT163 ...
The 'HC107 and 'HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These CD54HCT107 flip-flops have independent J, K, Reset and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS family.