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CD54HC85F3A

Features: • Buffered Inputs and Outputs• Typical Propagation Delay: 13ns (Data to Output at VCC = 5V, CL = 15pF, TA = 25oC• Serial or Parallel Expansion Without External Gating• Fanout (Over Temperature Range)- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads- ...

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SeekIC No. : 004311732 Detail

CD54HC85F3A: Features: • Buffered Inputs and Outputs• Typical Propagation Delay: 13ns (Data to Output at VCC = 5V, CL = 15pF, TA = 25oC• Serial or Parallel Expansion Without External GatingR...

CD54HC85F3A Data Sheet

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Part Number:
CD54HC85F3A
Supply Ability:
5000

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Product Details

Description



Features:

• Buffered Inputs and Outputs
• Typical Propagation Delay: 13ns (Data to Output at
  VCC = 5V, CL = 15pF, TA = 25oC
• Serial or Parallel Expansion Without External Gating
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
  VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1A at VOL, VOH


Pinout

Connection Diagram


Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .  -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . ±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . ±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . ±50mA


Description

The 'HC85 and 'HCT85 are high speed magnitude comparators that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.

These 4-bit devices compare two binary, BCD, or other monotonic codes and present the three possible magnitude results at the outputs (A > B, A < B, and A = B). The 4-bit input words are weighted (A0 to A3 and B0 to B3), where A3 and B3 are the most significant bits.

CD54HC85F3A are expandable without external gating, in both serial and parallel fashion. The upper part of the truth table indicates operation using a single device or devices in a serially expanded application. The parallel expansion scheme is described by the last three entries in the truth table.




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