CD54HC640F3A

The CD54HC640F3A is intended for two-way asynchronous communication between data buses. The feature of CD54HC640F3A are as follows: (1)buffered inputs; (2)three-state outputs; (3)applications in multiple-data-bus architecture; (4)fanout (over temperature range): standard outputs: 10 LSTTL loads, bus driver outputs: 15 LSTTL Loads; (5)wide operating temperature range: -55oC to 125oC; (6)balanced propagation delay and transition times; (7)significant power reduction compared to LSTTL logic ICs; (8)HC types: 2V to 6V operation, high noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V; (9)HCT types: 4.5V to 5.5V operation, direct LSTTL input logic compatibility, VIL= 0.8V (Max), VIH = 2V (Min); (10)CMOS Input compatibility, Il 1A at VOL, VOH.

The absolute maximum ratings of the CD54HC640F3A are: (1)DC supply voltage, VCC:  -0.5V to 7V; (2)DC input diode current, IIK for VI < -0.5V or VI > VCC + 0.5V: ±20mA; (3)DC output diode current, IOK for VO < -0.5V or VO > VCC + 0.5V: ±20mA; (4)DC drain current, per output, IO For -0.5V < VO < VCC + 0.5V: ±35mA; (5)DC output source or sink current per output pin, IO for VO > -0.5V or VO < VCC + 0.5V: ±25mA; (6)DC VCC or ground current, ICC: ±50mA.

The following is about the electrical characteristics of CD54HC640F3A: (1)High Level Input Voltage: 1.5V min; (2)Low Level Input Voltage: 0.5V max; (3)High Level Output Voltage CMOS Loads: 1.9V min; (4)High Level Output Voltage TTL Loads: 3.7V min; (5)Low Level Output Voltage CMOS Loads: 0.1V max; (6)Low Level Output Voltage TTL Loads: 0.4V max; (7)Input Leakage Current: ±1A max.