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CD54HC597

Features: • Buffered Inputs• Asynchronous Parallel Load• Fanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads• Wide Operating Temperature Range . . . -55to 125• Balance...

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SeekIC No. : 004311720 Detail

CD54HC597: Features: • Buffered Inputs• Asynchronous Parallel Load• Fanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Bus Driver Outputs . . . . . ....

CD54HC597 Data Sheet

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Part Number:
CD54HC597
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• Buffered Inputs
• Asynchronous Parallel Load
• Fanout (Over Temperature Range)
    Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55to 125
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
     2V to 6V Operation
     High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types
     4.5V to 5.5V Operation
     Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
     CMOS Input Compatibility, Il 1A at VOL, VOH


Pinout

Connection Diagram


Specifications

DC Supply Voltage, VCC .................................................................. -0.5V to 7V
DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V ..............±20mA
DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V .........±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V ............................................................25mA
DC VCC or Ground Current, ICC or IGND ..................................................±50mA




Description

The 'HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin-compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL is high.




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