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CD54HC4040

Features: • Fully Static Operation• Buffered Inputs• Common Reset• Negative Edge Pulsing• Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads• Wide Operatin...

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SeekIC No. : 004311692 Detail

CD54HC4040: Features: • Fully Static Operation• Buffered Inputs• Common Reset• Negative Edge Pulsing• Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . ....

CD54HC4040 Data Sheet

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Part Number:
CD54HC4040
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative Edge Pulsing
• Fanout (Over Temperature Range)
   - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
   - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
   - 2V to 6V Operation
   - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types
   - 4.5V to 5.5V Operation
   - Direct LSTTL Input Logic Compatibility,VIL= 0.8V (Max), VIH = 2V (Min)
   - CMOS Input Compatibility, Il 1A at VOL, VOH


Pinout

Connection Diagram


Specifications

DC Supply Voltage, VCC        . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
   For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
   For VO < -0.5V or VO > VCC + 0.5V . . . . . .   . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
   For VO > -0.5V or VO < VCC + 0.5V . . . . . . .   . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA


Description

The 'HC4040 and 'HCT4040 are 14-stage ripple-carry binary counters. All counter stages are master-slave flipflops.The state of the stage advances one count on the negative clock transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.




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