CD54HC4017

Features:

* Fully Static Operation
* Buffered Inputs
* Common Reset
* Positive Edge Clocking
* Typicalf_MAX  =50MHzatV_CC =5V,C_L =15pF,TA=25
* Fanout (Over Temperature Range)
   - Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
   - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
* Wide Operating Temperature Range . . . -55  to 125
* Balanced Propagation Delay and Transition Times
* Significant Power Reduction Compared to LSTTL Logic ICs
* HC Types
  - 2V to 6V Operation
  - High Noise Immunity: N_IL  = 30%, N _IH = 30% of V_CC at V_CC  = 5V



Pinout




Specifications

DC Supply Voltage, V_CC . . . . . . . . . . . . . . . . . . . . . . . ........... -0.5V to 7V
DC Input Diode Current, I_IK
    For V_II < -0.5V or V_CC  > V  + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I_OK
    For V _O < -0.5V or V _O > V _CC + 0.5V  . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I_O
   For V_O  > -0.5V or V_O  < V _CC + 0.5V    . . . . . . . . . . . . . . . . . . . .±25mA
DC V_CC  or Ground Current, I_CC I_GND. . . . . . . . . . . . . . . . ..............±50mA.


Description

The 'HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock period cycle. The CARRY (TC) output transitions low to high after OUTPUT 10 goes from high to low, and can be used in conjunction with the CLOCK ENABLE (CE) to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET (MR) input is also provided which when taken high sets all the decoded outputs, except "0", low.

CD54HC4017 can drive up to 10 low power Schottky equivalent loads.