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CD54HC377

Features: • Buffered Common Clock• Buffered Inputs• Typical Propagation Delay at CL = 15pF,VCC = 5V, TA = 25oC- 14 ns (HC Types- 16 ns (HCT Types)• Fanout (Over Temperature Range)- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads- Bus Driver Outputs . . . . . ....

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SeekIC No. : 004311682 Detail

CD54HC377: Features: • Buffered Common Clock• Buffered Inputs• Typical Propagation Delay at CL = 15pF,VCC = 5V, TA = 25oC- 14 ns (HC Types- 16 ns (HCT Types)• Fanout (Over Temperature R...

CD54HC377 Data Sheet

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Part Number:
CD54HC377
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Buffered Common Clock
• Buffered Inputs
• Typical Propagation Delay at CL = 15pF,VCC = 5V, TA = 25oC- 14 ns (HC Types- 16 ns (HCT Types)
• Fanout (Over Temperature Range)- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTLLogic ICs
• HC Types- 2V to 6V Operation- High Noise Immunity: NIL = 30%, NIH = 30%of VCC atVCC = 5V
• HCT Types- 4.5V to 5.5V Operation- Direct LSTTL Input Logic Compatibility,VIL= 0.8V (Max), VIH = 2V (Min)- CMOS Input Compatibility, Il 1A at VOL, VOH


Pinout

Connection Diagram


Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . .. . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . .  . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .  . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . .  . . . . .±50mA


Description

The 'HC377 and 'HCT377 are octal D-type flip-flops with abuffered clock (CP) common to all eight flip-flops. All the flipflopsare loaded simultaneously on the positive edge of theclock (CP) when the Data Enable (E) is Low.




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