CD54HC299

The 'HC259 and 'HCT299 are 8-bit shift/storage registers with three-state bus interface capability. The register has four synchronous-operating modes controlled by the two select
inputs as shown in the mode select (S0, S1) table. CD54HC299 select, the serial data (DS0, DS7) and the parallel data (I/O₀- I/O₇) respond only to the low-to-high transition of the clock (CP) pulse. S0, S1 and data inputs must be stable one setup time prior to the CD54HC299 clock positive transition.
The CD54HC299 Master Reset (MR) is an asynchronous active low input.When MR output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded
by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register, and tying the serial output (Q7) to the serial data (DS0) input of
the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage.
The three-state input/output I(/O) port has three modes of operation:
1. CD54HC299 Both output enable (OE1 and OE2) inputs are low and S0 or S1 or both are low, the data  in the register is presented at the eight outputs.
2. When both CD54HC299 S0 and S1 are high, I/O terminals are in the high impedance state but being input ports, ready for parallel data to be loaded into eight registers with one clock transition regardless of the status ofOE1 and OE2.
3. Either one of the two output enable inputs being high will force I/O terminals to be in the off-state. CD54HC299 is noted that each I/O terminal is a three-state output and a CMOS buffer input.