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CD54HC273

Features: • Common Clock and Asynchronous Master Reset• Positive Edge Triggering• Buffered Inputs• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25• Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Output...

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SeekIC No. : 004311666 Detail

CD54HC273: Features: • Common Clock and Asynchronous Master Reset• Positive Edge Triggering• Buffered Inputs• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25• Fanout (Over Te...

CD54HC273 Data Sheet

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Part Number:
CD54HC273
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
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  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Common Clock and Asynchronous Master Reset
• Positive Edge Triggering
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25
• Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55 to 125
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il 1mA at VOL, VOH


Pinout

Connection Diagram


Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . ...±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC  . . . . . . . . . . . . . . . . . . . . . . ±50mA 


Description

The 'HC273 and 'HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicon-gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits.

CD54HC273 Information at the D inputis transferred to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs are reset to a logic 0.




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