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CD54HC194

Features: * Four Operating Modes- Shift Right, Shift Left, Hold and Reset* Synchronous Parallel or Serial Operation* Typical fMAX= 60MHz at VCC= 5V, CL = 15pF,TA= 25* Asynchronous Master Reset* Fanout (Over Temperature Range)- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads- Bus Drive...

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SeekIC No. : 004311649 Detail

CD54HC194: Features: * Four Operating Modes- Shift Right, Shift Left, Hold and Reset* Synchronous Parallel or Serial Operation* Typical fMAX= 60MHz at VCC= 5V, CL = 15pF,TA= 25* Asynchronous Master Reset* Fano...

CD54HC194 Data Sheet

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Part Number:
CD54HC194
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
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Product Details

Description



Features:

* Four Operating Modes
- Shift Right, Shift Left, Hold and Reset
* Synchronous Parallel or Serial Operation
* Typical fMAX = 60MHz at VCC = 5V, CL  = 15pF,TA = 25
* Asynchronous Master Reset
* Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
* Wide Operating Temperature Range . . . -55 to 125
* Balanced Propagation Delay and Transition Times
* Significant Power Reduction Compared to LSTTL Logic ICs
* HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH= 30% of VCC at VCC  = 5V
* HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,VIL = 0.8V (Max), VIH  = 2V (Min)
- CMOS Input Compatibility, Il  1 A at VOL , VOH
   



Pinout

Connection Diagram


Specifications

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI  > V CC + 0.5v . . . . . . . . . . . . . . . . .. . .±20mA
DC Output Diode Current, IOK
For VO  < -0.5V or VO > VCC + 0.5V  . . . . . . . . . . . . . . .  . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V    . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICCor IGND . . . . . . . . . . . . . . . . .±50mA 


Description

   The 'HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR). In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data
entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing CD54HC194 register is accomplished by a Low applied to the Master Reset (MR) pin.




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