CD54HC175

• Common Clock and Asynchronous Reset on Four D-Type Flip-Flops
• Positive Edge Pulse Triggering
• Complementary Outputs
• Buffered Inputs
• Typical f_MAX = 50MHz at V_CC = 5V, C_L = 15pF, T_A = 25^oC
• Fanout (Over Temperature Range)
   - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
   - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
   - 2V to 6V Operation
   - High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
• HCT Types
   - 4.5V to 5.5V Operation
   - Direct LSTTL Input Logic Compatibility, V_IL= 0.8V (Max), V_IH = 2V (Min)
   - CMOS Input Compatibility, I_l 1A at V_OL, V_OH

The 'HC175 and 'HCT175 are high speed Quad D-type Flip- Flops with individual D-inputs and Q, Q complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.

CD54HC175 Information at the D input is transferred to the Q, Q outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q outputs to a logic 1.