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CD54HC174

Features: *Buffered Positive Edge Triggered Clock*Asynchronous Common Reset*Fanout (Over Temperature Range)-Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads-Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads*Wide Operating Temperature Range . . .-55 to 125*Balanced Propagation D...

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SeekIC No. : 004311642 Detail

CD54HC174: Features: *Buffered Positive Edge Triggered Clock*Asynchronous Common Reset*Fanout (Over Temperature Range)-Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads-Bus Driver Outputs . . . . . ....

CD54HC174 Data Sheet

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Part Number:
CD54HC174
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

*Buffered Positive Edge Triggered Clock
*Asynchronous Common Reset
*Fanout (Over Temperature Range)
-Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads
-Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads
*Wide Operating Temperature Range . . .-55 to 125
*Balanced Propagation Delay and Transition Times
*Significant Power Reduction Compared to LSTTL Logic ICs
*HC Types
-2V to 6V Operation
-High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
*HCT Types
-4.5V to 5.5V Operation
-Direct LSTTL Input Logic Compatibility,VIL = 0.8V (Max), VIH = 2V (Min)
-CMOS Input Compatibility, Il1A at VOL, VOH





Pinout

Connection Diagram


Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7V
DC Input Diode Current, IIK
For VI  < -0.5V or VI   > VCC + 0.5V. . . . . . . . . . . . . . .  . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC  + 0.5V . . . . . . . . . . . . . . . . . . . ±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO  > -0.5V or VO  < VCC  + 0.5V . . . . . . . . . . . . . . . . . . .±25mA
DC VCC  or Ground Current, ICCor IGND. . . . . . . . . . . . . . . . . .±50mA
   
 





Description

   The 'HC174 and 'HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops.They possess low power and speeds com parable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset.Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR input, when low, sets all outputs to a low state.

  Each output can drive ten low power Schottky TTL equivalent loads. The 'HCT174 is functional as well as, pin compatible to the 'LS174.




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