CD54HC164

Buffered Inputs
Asynchronous Master Reset
Typical f_MAX  = 60MHz at V_CC  = 5V, C_L = 15pF,
T_A = 25
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55 to 125
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTLLogic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH= 30% of V_CCat V  = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
  V_IL = 0.8V (Max), V_IH= 2V (Min)
- CMOS Input Compatibility, I₁ 1_UA_atV_OL,V_OH

^{The 'HC164 and 'HCT164 are 8-bit serial-in parallel-out shiftregisters with asynchronous reset. Data is shifted on thepositive edge of Clock (CP). A LOW on the Master Reset(MR) pin resets the shift register and all outputs go to theLOW state regardless of the input conditions. Two SerialData inputs (DS1 and DS2) are provided, either one can beused as a Data Enable control.}