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CD54HC109

Features: • Asynchronous Set and Reset• Schmitt Trigger Clock Inputs• Typical Propagation Delay = 18ns at VCC = 5V, CL = 15pF, TA = 25oC• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25 • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . ...

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SeekIC No. : 004311610 Detail

CD54HC109: Features: • Asynchronous Set and Reset• Schmitt Trigger Clock Inputs• Typical Propagation Delay = 18ns at VCC = 5V, CL = 15pF, TA = 25oC• Typical fMAX = 60MHz at VCC = 5V, CL...

CD54HC109 Data Sheet

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Part Number:
CD54HC109
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Asynchronous Set and Reset
• Schmitt Trigger Clock Inputs
• Typical Propagation Delay = 18ns at VCC = 5V, CL = 15pF, TA = 25oC
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25
• Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55  to 125
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il 1mA at VOL, VOH


Pinout

Connection Diagram


Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . ...±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC. . . . . . . . . . . . . . . . . . . . . . .±50mA 


Description

The 'HC109 and 'HCT109 are dual J-K flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).

The flip-flop is set and reset by active-low S and R, respectively. CD54HC109 low on both the set and reset inputs simultaneously will force both Q and Q outputs high.
However, both set and reset going high simultaneously results in an unpredictable output condition.




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