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CD54HC107

Features: • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times• Asynchronous Reset• Complementary Outputs• Buffered Inputs• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25 • Fanout (Over Temperature Range) - Stand...

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SeekIC No. : 004311608 Detail

CD54HC107: Features: • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times• Asynchronous Reset• Complementary Outputs• Buffered Inputs• ...

CD54HC107 Data Sheet

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Part Number:
CD54HC107
Supply Ability:
5000

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  • 1~5000
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Product Details

Description



Features:

• Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times
• Asynchronous Reset
• Complementary Outputs
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25
• Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55  to 125
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Ii 1mA at VOL, VOH


Pinout

Connection Diagram


Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . ...±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . ..±50mA 


Description

The 'HC107 and 'HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.

These flip-flops have independent J, K, Reset and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. CD54HC107 is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS family.




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