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CD54ACT164F3A

Features: • Buffered Inputs• Typical Propagation Delay- 6ns at VCC = 5V, TA = 25, CL = 50pF• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015• SCR-Latchup-Resistant CMOS Process and Circuit Design• Speed of Bipolar FAST™/AS/S with Significantly Reduced Power ...

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SeekIC No. : 004311565 Detail

CD54ACT164F3A: Features: • Buffered Inputs• Typical Propagation Delay- 6ns at VCC = 5V, TA = 25, CL = 50pF• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015• SCR-Latchup-Resistant CMOS P...

CD54ACT164F3A Data Sheet

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Part Number:
CD54ACT164F3A
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Buffered Inputs
• Typical Propagation Delay
- 6ns at VCC = 5V, TA = 25, CL = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
• SCR-Latchup-Resistant CMOS Process and Circuit Design
• Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50W Transmission Lines


Application

·Audio
·Automotive
·Broadband
·Digital Control
·Military
·Optical Networking
·Security
·Telephony
·Video & Imaging
·Wireless


Pinout

Connection Diagram


Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . ±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA


Description

The 'AC164 and 'ACT164 are 8-bit serial-in/parallel-out shift registers with asynchronous reset that utilize Advanced CMOS Logic technology. Data is shifted on the positive edge of the clock (CP). A LOW on the Master Reset (MR) pin resets the shift register and all outputs go to the LOW state regardless of the input conditions. Two Serial Data inputs (DS1 and DS2) are provided; either one can be used as a Data Enable control.




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