CD54AC2993A

The CD54AC299/3A and CD54ACT299/3A are three-state, 8-input universal shift/storage registers with common parallel I/O pins. CD54AC2993A utilize the Harris Advanced CMOS Logic technology. These registers have four synchronous operating modes controlled by the two select inputs as shown in the Mode Select (S0, S1) table. CD54AC2993A Select, the Serial Data (DS0, DS7), and the Parallel Data (I/O0 - I/O7) respond only to the LOW-to-HIGH transition of the clock pulse (CP). S0, S1 and Data inputs must be present one setup time prior to the positive transition of the clock.

The CD54AC2993A Master Reset (MR) is an asynchronous active-LOW input. When MR is LOW, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (QO) to the serial data (DS7) input of the preceding register, and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage.
The three-state input/output (I/O) port has three modes of operation

1. CD54AC2993A Both Output Enable (OE1 and OE2) inputs are LOW and S0 or S1 or both are LOW, the data in the register is present at the eight outputs.

2. When both S0 and S1 are HIGH, I/O terminals are in the high-impedance state but being input ports, ready for parallel data to be loaded into eight registers with one clock transition regardless of the status of OE1 and OE2.

3. Either one of the two Output Enable inputs being HIGH will force I/O terminals to be in the off state. CD54AC2993A is noted that each I/O terminal is a three-state output and a CMOS buffer input.

The CD54AC299/3A and CD54ACT299/3A are supplied in 20 lead dual-in-line ceramic packages (F suffix).