CD54AC161F3A

The CD54AC161F3A is designed as one kind of synchronous presettable binary counter that utilizes the harris advanced CMOS logic technology. A low on the master reset pin resets the shif register and all outputs go to the LOW state regardless of the input conditions.

Features of the CD54AC161F3A are:(1)Buffered Inputs;(2)Typical Propagation Delay 6.0 ns at VCC = 5V, TA = 25 , CL = 50 pF;(3)Exceeds 2kV ESD Protection MIL-STD-883, Method 3015;(4)SCR-Latchup-Resistant CMOS Process and Circuit Design;(5)Speed of Bipolar FAST/AS/S with Significantly Reduced Power Consumption;(6)Balanced Propagation Delays;(7)AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply;(8)±24 mA Output Drive Current: Fanout to 15 FAST ICs and Drives 50 Transmission Lines.

The absolute maximum ratings of the CD54AC161F3A can be summarized as:(1)DC Supply Voltage: -0.5V to 6V;(2)DC Input Diode Current For VI < -0.5V or VI > VCC + 0.5V: ±20 mA;(3)DC Output Diode Current For VO < -0.5V or VO > VCC + 0.5V: ±50 mA;(4)DC Output Source or Sink Current per Output Pin For VO > -0.5V or VO < VCC + 0.5V: ±50 mA;(5)DC VCC or Ground Current, ICC or IGND: ±100 mA. If you want to know more information such as the electrical characteristics about the CD54AC161F3A, please download the datasheet in www.seekic.com or www.chinaicmart.com .