CD4724BC

Features:

Wide supply voltage range: 3.0V to                           15V
High noise immunity:                                 0.45 VDD (typ.)
 Low power TTL                              fan out of 2 driving 74L
                      compatibility                          or 1 driving 74LS                               
Serial to parallel capability
Storage register capability
Random (addressable) data entry
Active high demultiplexing capability
Common active high clear


Pinout




Specifications

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Supply Voltage (V_DD).............. b0.5V to a18 V_DC
Input Voltage (V_IN) ............. .b0.5V to V_DD a0.5 V_DC
Storage Temperature (T_S).................... 65to 150
Power Dissipation (P_D)
Dual-In-Line .....................................700 mW
Small Outline .....................................500 mW
Lead Temperature (T_L)
(Soldering, 10 seconds) ...................................260


Description

The CD4724BC is an 8-bit addressable latch with threeaddress inputs (A0A2), an active low enable input (E),
active high clear input (CL), a data input (D) and eight out-puts (Q0Q7).

Data is entered into a particular bit in the latch when that isaddressed by the address inputs and the enable (E) isLOW. CD4724BC Data entry is inhibited when enable (E) is HIGH.When clear (CL) and enable (E) are HIGH, all outputs areLOW. When clear (CL) is HIGH and enable (E) is LOW, thechannel demultiplexing occurs. The bit that is addressedhas anactive output which follows the data input while allunaddressed bits are held LOW. When operating in theaddressable latch mode (E = CL = LOW), changing morethan one bit of the address could impose a transient wrongaddress. Therefore, this should only be done while in thememory mode (E = HIGH, CL = LOW).