CD4515BMS

Features:

* High-Voltage Types (20-Volt Rating)
* CD4514BMS Output "High" on Select
* CD4515BMS Output "Low" on Select
* Strobed Input Latch
* Inhibit Control
* 100% Tested for Quiescent Current at 20V
* Maximum Input Current of 1A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and 25
* Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
* 5V, 10V, and 15V Parametric Ratings
* Standardized, Symmetrical Output Characteristics
* Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
'B' Series CMOS Devices"


Application

* Digital Multiplexing
* Address Decoding
* Hexadecimal/BCD Decoding
* Program-counter Decoding
* Control Decoder


Pinout




Specifications

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55 to +125
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65 to +150
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265


Description

CD4514BMS and CD4515BMS consist of a 4-bit strobed latch and a 4-to-16-line decoder. The latches hold the last input data presented prior to the strobe transition from 1 to 0. Inhibit control allows all outputs to be placed at 0(CD4514BMS) or 1(CD4515BMS) regardless of the state of the data or strobe inputs.
The CD4515BMS decode truth table indicates all combinations of data inputs and appropriate selected outputs.
These devices are similar to industry types MC14514 and MC14515.
The CD4514BMS and CD4515BMS are supplied in these 24 lead outline packages:
Braze Seal DIP H4V
Frit Seal DIP H1Z
Ceramic Flatpack H4P