CD4504BMS

Features:

* High Voltage Type (20V Rating)
* Independence of Power Supply Sequence Consider-
ations
- VCC can Exceed VDD
- Input Signals can Exceed Both VCC and VDD
* Up and Down Level Shifting Capability
* Shiftable Input Threshold for Either CMOS or TTL
Compatibility
* 100% Tested for Quiescent Current at 20V
* 5V, 10V and 15V Parametric Ratings
* Standardized Symmetrical Output Characteristics
* Maximum Input Current of 1A at 18V Over Full Pack-
o
age Temperature Range; 100nA at 18V and +25 C
* Meets All Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
'B' Series CMOS Devices"




Pinout






Specifications

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . .. ..±10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55 to +125
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65 to +150
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265





Description

CD4504BMS hex voltage level shifter consists of six circuits which shift input signals from the VCC logic level to the VDD logic level. To shift TTL signals to CMOS logic levels, the SELECT input is at the VCC HIGH logic state. When the SELECT input is at a LOW logic state, each circuit translates signals from one CMOS level to another. The CD4504BMS is supplied in these 16-lead outline packages: Frit Seal DIP H1F Ceramic Flatpack H6W