CD4094BC

 Wide supply voltage range: 3.0V to 18V
High noise immunity: 0.45 V_DD (typ.)
 Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS
 3-STATE outputs

Supply Voltage (V_DD) ......................................................-0.5V to +18V
Input Voltage (V_IN) ................................................-0.5V to VDD +0.5V
Storage Temperature Range (TS) ..............................-65 to +150
Power Dissipation (P^_D)
Dual-In-Line ............................................................................700 mW
Small Outline ..........................................................................500 mW
Lead Temp. (T_L) (Soldering, 10 sec.).......................................... 260

The CD4094BC consists of an 8-bit shift register and a 3- STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage (Q_S) can be used to cascade several devices. Data on the QS output is transferred to a second output, Q¢S, on the following negative clock edge.

CD4094BC output of each stage of the shift register feeds a latch, which latches data on the negative edge of the STROBE input. When STROBE is HIGH, data propagates through the latch to 3-STATE output gates. These gates are enabled when OUTPUT ENABLE is taken HIGH.