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CD4086BMS

Features: • Medium Speed Operation - tPHL = 90ns; tPLH = 140ns (Typ.) at 10V• High Voltage Type (20V Rating)• INHIBIT and ENABLE Inputs• Buffered Outputs• 100% Tested for Quiescent Current at 20V• Maximum Input Current of 1µA at 18V Over Full Package Tempe...

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SeekIC No. : 004311351 Detail

CD4086BMS: Features: • Medium Speed Operation - tPHL = 90ns; tPLH = 140ns (Typ.) at 10V• High Voltage Type (20V Rating)• INHIBIT and ENABLE Inputs• Buffered Outputs• 100% Tested f...

CD4086BMS Data Sheet

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Part Number:
CD4086BMS
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Medium Speed Operation - tPHL = 90ns; tPLH = 140ns (Typ.) at 10V
• High Voltage Type (20V Rating)
• INHIBIT and ENABLE Inputs
• Buffered Outputs
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"


Pinout

Connection Diagram


Specifications

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . ...................... . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . .  .....................-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . .. . . . ..................... . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . . ..................... . . . -55 to +125
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . ..................... -65 to +150
Lead Temperature (During Soldering) . . . . . . . . . . . . . ..................... . .  +265
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum


Description

CD4086BMS contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/EXP input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/EXP is tied to VSS and ENABLE/EXP to VDD. See Figure 2 and its associated explanation for applications where a capability greater than 4-wide is required.

The CD4076B is supplied in these 14 lead outline packages:
Braze Seal DIP H4H
Frit Seal DIP H1B
Ceramic Flatpack H4F




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