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CD4073BMS

Features: • High-Voltage Types (20V Rating)• CD4073BMS Triple 3-Input AND Gate• CD4081BMS Quad 2-Input AND Gate• CD4082BMS Dual 4-Input AND Gate• Medium Speed Operation:- tPLH, tPHL = 60ns (typ) at VDD = 10V• 100% Tested for Quiescent Current at 20V• Maxim...

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SeekIC No. : 004311338 Detail

CD4073BMS: Features: • High-Voltage Types (20V Rating)• CD4073BMS Triple 3-Input AND Gate• CD4081BMS Quad 2-Input AND Gate• CD4082BMS Dual 4-Input AND Gate• Medium Speed Operation...

CD4073BMS Data Sheet

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Part Number:
CD4073BMS
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• High-Voltage Types (20V Rating)
• CD4073BMS Triple 3-Input AND Gate
• CD4081BMS Quad 2-Input AND Gate
• CD4082BMS Dual 4-Input AND Gate
• Medium Speed Operation:
- tPLH, tPHL = 60ns (typ) at VDD = 10V
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package
Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
'B' Series CMOS Devices"


Pinout

Connection Diagram


Specifications

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . .. .. .. .. .. .. .. .. -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . .. .. .. .. .. ... .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . .. .. ... . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . . . . .. .. .. .. .. ... . . -55 to +125
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . .. .. .. .. .. .... . -65to +150
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . .. .... ... .. .. . +265
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for10s Maximum


Description

CD4073BMS, CD4081BMS and CD4082BMS AND gates provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates. The CD4073BMS, CD4081BMS and CD4082BMS are supplied in these 14 lead outline packages:
Braze Seal DIP *H4Q †H4H Frit Seal DIP
*H1B Ceramic Flatpack
*H3W
*CD4073B, CD4081B †CD4082B




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