Features: • High Voltage Type (20V Rating)
• Medium Speed Operation:
TPHL, TPLH = 75ns (Typ.) at VDD = 10V
• Buffered Inputs and Outputs
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range):
1V at VDD = 5V
2V at VDD = 10V
SpecificationsDC Supply Voltage Range, (VDD)..................................-0.5V to +20V (Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs .........................................................................................0.5V to VDD +0.5V
DC Input Current, Any One Input ...........................................................................................................10mA
Operating Temperature Range......................................................-55oC to +125oC Package Types D, F, K, H
Storage Temperature Range (TSTG)......................................................................................-65oC to +150oC
Lead Temperature (During Soldering).................................................................................................. +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance ....ja,jc
Ceramic DIP and FRIT Package ..............................................................................................80oC/W, 20oC/W
Flatpack Package................................70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . ....................................................................... . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . ......................Derate Linearity at 12mW/oC to 200mW
Device Dissipation per Output Tr..........100mW For TA = Full Package Temperature Range (All Package Types)
Junction Temperature ......................................................................................................................... +175oC
DescriptionCD4068BMS NAND/AND gate provides the system designer with direct implementation of the positive logic 8 Input NAND and AND functions and supplements the existing family of CMOSgates.
The CD4068BMS is supplied in these 14 lead outline packages:
Braze Seal DIP H4H
Frit Seal DIP H1B
Ceramic Flatpack H3W
CD4068BMS Data Sheet
