CD4042BC

Features: Wide supply voltage range3.0V to 15V High noise immunity 0.45 VDD (typ.) Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS Clock polarity control Fully buffered data inputs Q and Q outputsSpecificationsIf Military/Aerospace specified devices are required, please cont...

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CD4042BC Picture
SeekIC No. : 004311275 Detail

CD4042BC: Features: Wide supply voltage range3.0V to 15V High noise immunity 0.45 VDD (typ.) Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS Clock polarity control Fully buffered data i...

floor Price/Ceiling Price

Part Number:
CD4042BC
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

 Wide supply voltage range                    3.0V to 15V
High noise immunity                         0.45 VDD (typ.)
Low power TTL                    Fan out of 2 driving 74L
   compatibility                                  or 1 driving 74LS
Clock polarity control
Fully buffered data inputs
Q and Q outputs



Specifications

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (VDD)                                 -0.5V to +18V
Input Voltage (VIN)                           -0.5V to VDD +0.5V
Storage Temperature Range (TS)            -65to +150
Power Dissipation (PD)
   Dual-In-Line                                                    700 mW
   Small Outline                                                   500 mW
Lead Temperature (TL)
(Soldering, 10 seconds)                                         260



Description

The CD4042BM/CD4042BC quad clocked ``D'' latch is a monolithic complementary MOS (CMOS) integrated circuit constructed with P- and N-channel nhancement mode transistors. The outputs Q and Q either latch or follow the data input depending on the clock level which is pro-grammed by the polarity input. For polarity e 0; the CD4042BC informa- tion present at the data input is transferred to Q and Q during 0 clock level; and for polarity e 1, the transfer occurs during the 1 clock level. When a clock transition occurs (positive for polarity e 0 and negative for polarity e 1), the CD4042BC information present at the input during the clock transition is retained at the outputs until an opposite clock transition oc-curs.




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