Features: Wide supply voltage range3.0V to 15V High noise immunity 0.45 VDD (typ.) Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS Clock polarity control Fully buffered data inputs Q and Q outputsSpecificationsIf Military/Aerospace specified devices are required, please cont...
CD4042BC: Features: Wide supply voltage range3.0V to 15V High noise immunity 0.45 VDD (typ.) Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS Clock polarity control Fully buffered data i...
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The CD4042BM/CD4042BC quad clocked ``D'' latch is a monolithic complementary MOS (CMOS) integrated circuit constructed with P- and N-channel nhancement mode transistors. The outputs Q and Q either latch or follow the data input depending on the clock level which is pro-grammed by the polarity input. For polarity e 0; the CD4042BC informa- tion present at the data input is transferred to Q and Q during 0 clock level; and for polarity e 1, the transfer occurs during the 1 clock level. When a clock transition occurs (positive for polarity e 0 and negative for polarity e 1), the CD4042BC information present at the input during the clock transition is retained at the outputs until an opposite clock transition oc-curs.