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CD4040BCM

Counter Shift Registers 12-Stage Binary Ctr

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SeekIC No. : 00421370 Detail

CD4040BCM: Counter Shift Registers 12-Stage Binary Ctr

CD4040BCM Data Sheet

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Part Number:
CD4040BCM
Mfg:
Fairchild Semiconductor
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/17

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Product Details

Quick Details

Counter Type : Binary Counting Sequence : Up
Number of Circuits : 1 Package / Case : SOIC-16
Logic Family : CD4000 Logic Type : CMOS
Number of Input Lines : 1 Propagation Delay Time : 550 ns, 210 ns, 150 ns
Maximum Operating Temperature : + 125 C Minimum Operating Temperature : - 55 C
Packaging : Tube    

Description

Output Type :
Package / Case : SOIC-16
Number of Circuits : 1
Maximum Operating Temperature : + 125 C
Minimum Operating Temperature : - 55 C
Logic Type : CMOS
Packaging : Tube
Counter Type : Binary
Counting Sequence : Up
Number of Input Lines : 1
Logic Family : CD4000
Propagation Delay Time : 550 ns, 210 ns, 150 ns


Features:

· Wide supply voltage range: 3.0V to 15V
· High noise immunity: 0.45 VDD (typ.)
· Low power TTL compatibility: Fan out of 2 driving 74L
   or 1 driving 74LS
· Medium speed operation: 8 MHz typ. at VDD = 10V
· Schmitt trigger clock in


Pinout

Connection Diagram


Specifications

Supply Voltage (VDD) .................................−0.5V to +18V
Input Voltage (VIN) ............................−0.5V to VDD +0.5V
Storage Temperature Range (TS)......... −65°C to +150°C
Package Dissipation (PD)
Dual-In-Line ........................................................700 mW
Small Outline .......................................................500 mW
Lead Temperature (TL)
(Soldering, 10 seconds)........................................ 260°C


Description

The CD4020BC, CD4060BC are 14-stage ripple carry binary counters, and the CD4040BC is a 12-stage ripple carry binary counter. The counters are advanced one count on the negative transition of each clock pulse. The CD4020BC counters are reset to the zero state by a logical "1" at the reset input independent of clock.




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