CD4024BMS

Features:

• High Voltage Types (20V Rating)
• Medium Speed Operation
• Fully Static Operation
• Buffered Inputs and Outputs
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• Common Reset
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1a at 18V Over Full Package- Temperature Range;
- 100nA at 18V and 25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications For Description Of 'B' Series CMOS Devices"




Application

• Control Counters
• Timers
• Frequency Dividers
• Time-Delay Circuits




Pinout






Specifications

DC Supply Voltage Range, (V_DD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (T_STG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum




Description

CD4020BMS - 14 Stage CD4024BMS - 7 Stage CD4040BMS - 12 Stage CD4020BMS, CD4024BMS, and CD4040BMS are ripplecarry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered. The CD4020BMS, CD4024BMS and the CD4040BMS is supplied in these 14 lead outline packages: CD4020B CD4024B CD4040B Braze Seal DIP H4W H4Q H4X Frit Seal DIP H1F H1B H1F Ceramic Flatpack H6W H3W H6W