Features: • High Voltage Types (20V Rating)
• One Input and Two Output Buses
• Unlimited Expansion in Bit and Word Directions
• Data Lines have Latched Inputs
• 3-State Outputs
• Separate Control of Each Bus, Allowing Simultaneous Independent Reading of any of Four Registers on Bus A and Bus B and Independent Writing Into any of the Four Registers
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1A at 18V Over Full Package
Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Full Package-Temperature Range):
1V at VDD = 5V
2V at VDD = 10V
2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standards No. 13B, "Standard Specifications for Description of "B" Series CMOS Devices"
Application• Scratch Pad Memories
• Arithmetic Units
• Data Storage
Pinout
SpecificationsDC Supply Voltage Range, (VDD) .... -0.5V to +20V (Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs .............................................................0.5V to VDD +0.5V
DC Input Current, Any One Input .............................................................................±10mA
Operating Temperature Range......................... -55 to +125 Package Types D, F, K, H
Storage Temperature Range (TSTG) ....................................................... -65to +150
Lead Temperature (During Soldering) ................................................................... +265
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s MaximumDescriptionThe CD40208BMS is a 4 x 4 multiport register containing four 4-bit registers, write address decoder, two separate read address decoders, and two 3-state output buses. When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high impedance state. The high impedance third state provides the outputs with the capability of being connected to the bus lines in a bus organized system without the need for interface or pull-up components.
When the WRITE ENABLE input is high, all data input lines are latched on the positive transition of the CLOCK and the data is entered into the word selected by the write address lines. When WRITE ENABLE is low, the CLOCK is inhibited and no new data is entered. In either case, the CD40208BMS contents of any word may be accessed via the read address lines independent of the state of the CLOCK input.
The CD40208BMS types are supplied in hermetic 24-lead dual-in-line ceramic packages (D and F suffixes), 24-lead dual-in-line plastic packages (E suffix), 24-lead ceramic flat packages (K suffix), and in chip form (H suffix). The CD40208BMS is supplied in these 24-lead outline packages:
Braze Seal DIP HNZ
Ceramic Flatpack H4P
CD40208BMS Data Sheet
