CD4017BCM

Counter Shift Registers Decode Ctr/Divider

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CD4017BCM Picture
SeekIC No. : 00421824 Detail

CD4017BCM: Counter Shift Registers Decode Ctr/Divider

floor Price/Ceiling Price

Part Number:
CD4017BCM
Mfg:
Fairchild Semiconductor
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Quick Details

Counter Type : Decade Counting Sequence : Up
Number of Circuits : 1 Package / Case : SOIC-16
Logic Family : CD4000 Logic Type : CMOS
Number of Input Lines : 1 Propagation Delay Time : 1000 ns, 400 ns, 320 ns
Maximum Operating Temperature : + 125 C Minimum Operating Temperature : - 55 C
Packaging : Rail    

Description

Output Type :
Package / Case : SOIC-16
Number of Circuits : 1
Maximum Operating Temperature : + 125 C
Minimum Operating Temperature : - 55 C
Logic Type : CMOS
Counting Sequence : Up
Number of Input Lines : 1
Logic Family : CD4000
Counter Type : Decade
Packaging : Rail
Propagation Delay Time : 1000 ns, 400 ns, 320 ns


Features:

` Wide supply voltage range: 3.0V to 15V
` High noise immunity: 0.45 VDD (typ.)
` Low power Fan out of 2 driving 74L
  TTL compatibility: or 1 driving 74LS
` Medium speed operation: 5.0 MHz (typ.)
  with 10V VDD
` Low power: 10 W (typ.)
` Fully static operation



Application

• Automotive
• Instrumentation
• Medical electronics
• Alarm systems
• Industrial electronics
• Remote metering



Pinout

  Connection Diagram


Specifications

DC Supply Voltage (VDD) .....−0.5 VDC to +18 VDC
Input Voltage (VIN) .....−0.5 VDC to VDD +0.5 VDC
Storage Temperature (TS) .........−65°C to +150°C
Power Dissipation (PD)
Dual-In-Line .............................................700 mW
Small Outline............................................ 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) ..............................260°C



Description

The CD4017BC is a 5-stage divide-by-10 Johnson counter with 10 decoded outputs and a carry out bit. The CD4022BC is a 4-stage divide-by-8 Johnson counter with 8 decoded outputs and a carry-out bit.

These CD4017BC counters are cleared to their zero count by a logical "1" on their reset line. These counters are advanced on the positive edge of the clock signal when the clock enable signal is in the logical "0" state.

The configuration of the CD4017BC and CD4022BC permits medium speed operation and assures a hazard free counting sequence. The 10/8 decoded outputs are normally in the logical "0" state and go to the logical "1" state only at their respective time slot. Each decoded output remains high for 1 full clock cycle. The carry-out signal completes a full cycle for every 10/8 clock input cycles and is used as a ripple carry signal to any succeeding stages.




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