Counter Shift Registers Decode Ctr/Divider
CD4017BCM: Counter Shift Registers Decode Ctr/Divider
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Counter Type : | Decade | Counting Sequence : | Up |
Number of Circuits : | 1 | Package / Case : | SOIC-16 |
Logic Family : | CD4000 | Logic Type : | CMOS |
Number of Input Lines : | 1 | Propagation Delay Time : | 1000 ns, 400 ns, 320 ns |
Maximum Operating Temperature : | + 125 C | Minimum Operating Temperature : | - 55 C |
Packaging : | Rail |
The CD4017BC is a 5-stage divide-by-10 Johnson counter with 10 decoded outputs and a carry out bit. The CD4022BC is a 4-stage divide-by-8 Johnson counter with 8 decoded outputs and a carry-out bit.
These CD4017BC counters are cleared to their zero count by a logical "1" on their reset line. These counters are advanced on the positive edge of the clock signal when the clock enable signal is in the logical "0" state.
The configuration of the CD4017BC and CD4022BC permits medium speed operation and assures a hazard free counting sequence. The 10/8 decoded outputs are normally in the logical "0" state and go to the logical "1" state only at their respective time slot. Each decoded output remains high for 1 full clock cycle. The carry-out signal completes a full cycle for every 10/8 clock input cycles and is used as a ripple carry signal to any succeeding stages.