CD40174BC

Features: Wide supply voltage range: 3V to 15V High noise immunity: 0.45 VDD (typ.) Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74 LS Equivalent to MC14174B, MC14175B Equivalent to MM74C174, MM74C175SpecificationsDC Supply Voltage (VDD) -0.5V to +18VInput Voltage (VIN)-0.5V...

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CD40174BC Picture
SeekIC No. : 004311201 Detail

CD40174BC: Features: Wide supply voltage range: 3V to 15V High noise immunity: 0.45 VDD (typ.) Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74 LS Equivalent to MC14174B, MC14175B Equival...

floor Price/Ceiling Price

Part Number:
CD40174BC
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description



Features:

 Wide supply voltage range: 3V to 15V
  High noise immunity: 0.45 VDD (typ.)
  Low power TTL compatibility:
        fan out of 2 driving 74L or 1 driving 74 LS
  Equivalent to MC14174B, MC14175B
  Equivalent to MM74C174, MM74C175



Specifications

DC Supply Voltage (VDD)                          -0.5V to +18V
Input Voltage (VIN)                       -0.5V to VDD +0.5VDC
Storage Temperature Range (TS)        -65°C to +150°C
Power Dissipation (PD)
Dual-In-Line                                                      700 mW
Small Outline                                                     500 mW
Lead Temperature (TL)
(Soldering, 10 seconds)                                      260°C



Description

The CD40174BC consists of six positive-edge triggered Dtype flip-flops; the true outputs from each flip-flop are externally available. The CD40175BC consists of four positiveedge triggered D-type flip-flops; both the true and complement outputs from each flip-flop are externally available.

All flip-flops are controlled by a common clock and a common clear. CD40174BC Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear input, clears all Q outputs to logical "0" and Q s (CD40175BC only) to logical "1".

All CD40174BC inputs are protected from static discharge by diode clamps to VDD and VSS.


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