CD40161BMS

Features:

• High-Voltage Types (20V Rating)
• CD40160BMS Decade with Asynchronous Clear
• CD40161BMS Binary with Asynchronous Clear
• CD40162BMS Decade with Synchronous Clear
• CD40163BMS Binary with Synchronous Clear
• Internal Look-Ahead for Fast Counting
• Carry Output for Cascading
• Synchronously Programmable
• Clear Asynchronous Input (CD40160BMS, CD40161BMS)
• Clear Synchronous Input (CD40162BMS, CD40163BMS)
• Synchronous Load Control Input
• Low Power TTL Compatibility
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package
   Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard No. 13B,
"Standard Specifications for Description of 'B' Series CMOS Devices"


Application

• Programmable Binary and Decade Counting
• Counter Control/Timers
• Frequency Dividing


Pinout




Specifications

DC Supply Voltage Range, (VDD). . . . . . . . . . . . . .-0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . .  .-0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range  . . . . . . . . .  . -55^o  C to +125^o C
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . -65^o C to +150^o C
Lead Temperature (During Soldering) . . . . . . . .  . . . . . . +265^o C

Description

CD40160BMS, CD40161BMS, CD40162BMS and CD40163BMS are 4-bit synchronous programmable counters. The CLEAR function of the CD40162BMS and CD40163BMS is synchronous and a low level at the CLEAR input sets all four outputs low on the next positive CLOCK edge. The CLEAR function of the CD40160BMS and CD40161BMS is asychronous and a low level at the CLEAR input sets all four outputs low regardless of the state of the CLOCK, LOAD, or ENABLE inputs. A low level at the LOAD input disables the counter and causes the output to agree with the setup data after the next CLOCK pulse regardless of the conditions of the ENABLE inputs.