Counter Shift Registers Dl 4-Bit Shift Reg
CD4015BCN: Counter Shift Registers Dl 4-Bit Shift Reg
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Counting Sequence : | Serial to Parallel | Number of Circuits : | 2 | ||
Package / Case : | PDIP W | Logic Family : | CD4000 | ||
Logic Type : | CMOS | Number of Input Lines : | 1 | ||
Propagation Delay Time : | 350 ns, 160 ns, 120 ns | Maximum Operating Temperature : | + 125 C | ||
Minimum Operating Temperature : | - 55 C | Packaging : | Rail |
The CD4015BC contains two identical, 4-stage, serialinput/ parallel-output registers with independent "Data", "Clock," and "Reset" inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A logic high on the "Reset" input resets all four stages covered by that input. All inputs are protected from static discharge by a series resistor and diode clamps to VDD and VSS.