DescriptionThe CD4011B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates.All inputs and outputs are buffered.It is supplied in 14-lead hermetic dual-in-line ceramic packages(D and F suffixes), 14-lead dual-in-lin...
CD4011B: DescriptionThe CD4011B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates.All inputs and outputs are buffered.It ...
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The CD4011B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates.All inputs and outputs are buffered.It is supplied in 14-lead hermetic dual-in-line ceramic packages(D and F suffixes), 14-lead dual-in-line plastic packages(E suffix), and in chip form(H suffix).
Features of the CD4011B are:(1)100% tested for quiescent current at 20 V; (2)maximum input current of 1 uA at 18 V over full package-temperature range;100 nA at 18 V and 25; (3)5 V , 10 V and 15 V parametric ratings.
The absolute maximum ratings of the CD4011B can be summarized as:(1): DC supply-voltage range(VDD) is -0.5 V to +20 V(voltages referenced to Vss terminal); (2): input voltage range, all inputs is -0.5 V to VDD+0.5 V; (3): DC input current, any one input is ±10 mA; (4): operating temperature range(Ta) is -55 to +125; (5): storage temperature range(Tstg) is -65 to +150.