Features: • High Voltage Type (20V Rating)
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1A at 18V Over Full Package
Temperature Range; 100nA at 18V and +25
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for
Description of 'B' Series CMOS Devices"
Application• High or Low Level Shifting with Three-State Outputs for Unidirectional or Bidirectional Bussing
• Isolation of Logic Subsystems Using Separate Power Supplies from Supply Sequencing, Supply Loss and Supply Regulation ConsiderationsPinout
SpecificationsDC Supply Voltage Range, (VDD) . . . . . . . . . . .. . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . . . . . . . .. . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . .. . . . . . . . . . . . . . -55 to +125
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . .. . . . . . . . . . . . . . . -65 to +150
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . .. . . . . . . . . . +265
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s MaximumDescriptionCD40109BMS contains four low-to-high voltage level shifting circuits. Each circuit will shift a low voltage digital logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a higher voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.
The CD40109BMS, unlike other low-to-high level shifting circuits, does not require the presence of the high voltage supply (VDD) before the application of either the low voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109BMS will operate as a high-to-low
level shifter.
The CD40109BMS also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high impedance state in the corresponding output.
The CD40109BMS is supplied in these 16-lead outline packages:
Braze Seal DIP.... H4T
Frit Seal DIP .....H1E
Ceramic Flatpack ..H6W
CD40109BMS Data Sheet
