CD40101BMS

Features: • High Voltage Type (20V Rating)• 100% Tested for Quiescent Current at 20V• 5V, 10V and 15V Parametric Ratings• Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25• Noise Margin (Over Full Package/Temperature Range)- ...

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CD40101BMS Picture
SeekIC No. : 004311161 Detail

CD40101BMS: Features: • High Voltage Type (20V Rating)• 100% Tested for Quiescent Current at 20V• 5V, 10V and 15V Parametric Ratings• Maximum Input Current of 1A at 18V Over Full Package...

floor Price/Ceiling Price

Part Number:
CD40101BMS
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

• High Voltage Type (20V Rating)
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1A at 18V Over Full Package
  Temperature Range; 100nA at 18V and +25
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for
  Description of 'B' Series CMOS Devices"



Pinout

  Connection Diagram


Specifications

DC Supply Voltage Range, (VDD) . . . . . . . . . . .. . . . .  . . . . .  . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . . . . . . . .. . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . .. . . . . .  . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . .. . . . . . . . . . . . . . -55 to +125
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . .. . . . . . . . . .  . . . . . -65 to +150
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . .. . . . . . . . . . +265
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum



Description

The CD40101BMS is a 9-bit (8 data bits plus 1 parity bit) parity generator/checker. It may be used to detect errors in data transmission or data retrieval. Odd and even outputs facilitate odd or even parity generation and checking.

When used as a parity generator, a parity bit is supplied along with the data to generate an even or odd parity output. When CD40101BMS used as a parity checker, the received data bits and parity bits are compared for correct parity. The even or odd outputs are used to indicate an error in the received data.

Word length capability is expandable by cascading. The CD40101BMS is also provided with an inhibit control. If the inhibit control is set at logical "1", the even and odd outputs go to a logical "0".

The CD40101BMS is supplied in these 14 lead outline packages:

Braze Seal DIP.. . H4H
Frit Seal DIP..... H1B
Ceramic Flatpack.. H3W


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