CD1284

Features:

High-speed, bidirectional, multi-protocol parallel port:
`Hardware implementation of all modes of the IEEE STD (Standard) 1284 specification (including automatic negotiation)
-Centronics-compatible mode
-Reverse Byte mode
-Reverse Nibble mode
-ECP (extended capabilities port) mode with run-length encoding/decoding
-EPP (enhanced parallel port) mode
-Up to 2-Mbytes/sec. transfer rate in ECP and EPP modes
`64-byte parallel FIFO with DMA interface Serial channel asynchronous protocol support to 115.2 kbps (register-setcompatible and functionally identical to CD1400)
-Twelve-byte FIFOs for each transmitter and receiver with programmable threshold for receive FIFO interrupt generation
-Improved interrupt schemes: Good Data^TM interrupts eliminate the need for character status check
-User-programmable and automatic flow control for serial channels
-Special character recognition and generation.
-Special character processing, particularly useful for UNIX^® environments, optionally handled automatically by the serial channels.
-Six modem control signals per channel (DTR, DSR, RTS, CTS, CD, and RI)


Pinout




Specifications

• Supply voltage (V_CC).................... +7.0 V (volts)
• Input voltages, with respect to ground....... -0.5 V to V_CC +0.5 V
• Operating temperature (T_A)..................0 to 70
• Storage temperature.................. .-65 to 150
• Power dissipation.................... .0.25 W (watt)


Description

The CD1284 can be described as a small computer system designed for the purpose of sending and receiving both serial and parallel data. It comprises a RISC processor (Multi-Channel Processing Unit or MPU), RAM, ROM, local CPU bus interface logic, two serial data channels, and one IEEE 1284-compliant parallel port with a specialized data pipeline designed for high-speed transfers.

Architecturally, the CD1284 is two devices merged into a single unit. One part is a modified, twochannel version of the Intel CD1400. The other part is a specialized parallel interface port supported by its own deep FIFO and DMA interface logic. The interrupt structure of the CD1400 has been enhanced to include the interrupt requirements of the parallel port. This section describes the modified CD1400 core and overall device architecture. Further sections provide details specific to the parallel channel. Chapter 7.0 provides detailed bit descriptions and encoding for the registers discussed in this chapter.

The MPU iCD1284 s a true RISC processor. In addition to having compact and efficient instructions, the MPU has a 'windowed' architecture that allows it to handle one channel and its registers at a time. Before beginning operations on a given channel, it loads an internal Index register that forces all accesses to the appropriate set of registers. CD1284 Index register becomes part of the internal address and allows direct addressing of the register bank and all hardware resources of the selected channel. No address computation is required to select the proper channel.

This same windowed scheme is carried through to the CPU interface as well (Figure 4). For all channel-specific accesses, the CPU first loads the CAR (Channel Access register) with a pointer to the channel to be accessed. Thereafter, all read and write operations occur with the proper channel. CD1284 software defines the register address once and this is valid for all channels because the CAR is part of the internal addressing.

This section presents a complete and detailed description of each register. Registers have two formats: 1) full eight bits, where the entire content defines a single function; 2)CD1284 register is a collection of bits, grouped singly or in multiples, defining a function. In the second format, the descriptions divide the register into CD1284's component parts and describe the bits individually. The order of register presentation corresponds to the register summary tables in Chapter 4.0.