CBT3857

Features:

• Enable signal is SSTL_2 compatible
• Optimized for use in Double Data Rate (DDR) SDRAM applications
• Flow-through architecture optimizes PCB layout
• Designed to be used with 200 Mbps
• Switch on resistance is designed to eliminate the need for series resistor to DDR SDRAM
• Internal 10 k pull-down resistors on B port
• Internal 50 k pull-up resistor on output enable input
• Full DDR solution provided when used with SSTL16857 and PCK857
• Latch-up protection exceeds 500 mA per JESD78
• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101


Pinout




Specifications

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DC supply voltage		0.5 to +4.6	V
IIK	DC input clamp current	VI/O < 0	50	mA
VI	DC input voltage range (OE only)2		VCC + 0.5	V
Tstg	Storage temperature range		65 to 150
VI	DC input voltage range (except OE)2		0.5 to 4.6	V

Description

This 10-bit bus switch CBT3857 is designed for 3 V to 3.6 V V_CC operation and SSTL_2 output enable (OE input levels.

When OE is LOW, the 10-bit bus switch is on and port A is connected to port B. When OE is HIGH, the switch is open, and a high-impedance state exists between the two ports.

The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The CBT3857 is characterized for operation from 0 to +85.