CB65000

The CB65000 standard cell series uses a high performance, low-voltage, 0.18 m drawn, six metal levels, high density and high speed HCMOS8D process.

CB65000 With an average routed gate density of 85,000 gates/mm², the CB65000 family allows the integration of up to 30 million equivalent gates and is ideal for high-complexity or high-performance devices for computer, telecommunication and consumer products.

CB65000 With a gate delay of 35 ps with High Performance transistor and 60 ps with Low Leakage transistor (for a 2-input NAND gate at fan-out 1), the library meets the most demanding speed requirements in telecommunication and
computer application designs today.

CB65000 Optimized for 1.8 V operation, the library features a power consumption of less than 35 nW/Gate/MHz (High Performance; fan-out=1) and 25 nW/Gate/MHz (Low Leakage; fan-out=1) at 1.8 V.

CB65000 I/O buffers can be fully configured for both 1.8 V and 3.3 V interface options, with several high speed buffer types available. These include: low voltage differential (LVDS) I/Os, PCI, AGP, USB, LVTTL, LVCMOS and SSTL.

CB65000 pad pitch down to 50 m, in a staggered arrangement, meets the requirements of high pin-count devices which tend to become pad-limited at such library densities. For very high pin-count ICs, advanced solutions such as Ball Grid Array packages are available.

New packaging solutions using a flip-chip approach are currently being developed.