CAT1026WE-25TE13

The CAT1026WE-25TE13 is one member of the CAT1026 series.The CAT1026 is complete memory and supervisory solution for microcontroller-based systems.A 2k-bit serial EEPROM memory and a system power supervisor with brown-out protection are integrated together in low power CMOS technology. Memory interface is via a 400kHz I2C bus.The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are programmable in metal and the default is 1010.

Features of the CAT1026WE-25TE13 are:(1)low power CMOS technology; (2)16-Byte page write buffer; (3)built-in inadvertent write protection; (4)1,000,000 Program/Erase cycles; (5)manual reset capability; (6)100 year data retention; (7)industrial and extended temperature ranges; (8)3.0 V to 5.5 V operation.The on-chip 2k-bit EEPROM memory features a 16-byte page. In addition, hardware data protection is provided by a VCC sense circuit that prevents writes to memory whenever VCC falls below the reset threshold or until VCC reaches the reset threshold during power up.

The absolute maximum ratings of the CAT1026WE-25TE13 can be summarized as:(1)voltage on any pin with respect to ground:-2.0 to Vcc+2.0V;(2)VCC with respect to ground:2.0V to +7.0V;(3)storage temperature:-65 to 150;(4)CAT1026WE-25TE13 temperature under bias:55 to +125;(5)CAT1026WE-25TE13 package power dissipation:1.0W.Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.In this condition an internal write cycle to the memory can not be started, but an in progress internal non-volatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5ms) before VCC reaches the minimum value of 2 V.