Features: • CMOS Low Power with SOS Speed (Typ). . . . . . . . 150mW
• Parallel Conversion Technique
• 15MHz Sampling Rate (Conversion Time) . . . . . . . 67ns
• 8-Bit Latched Three-State Output with Overflow Bit
• Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 LSB
• Single Supply Voltage . . . . . . . . . . . . . . . . . . 4V to 7.5V
• 2 Units in Series Allow 9-Bit Output
• 2 Units in Parallel Allow 30MHz Sampling RateApplication• TV Video Digitizing (Industrial/Security/Broadcast)
• High Speed A/D Conversion
• Ultrasound Signature Analysis
• Transient Signal Analysis
• High Energy Physics Research
• General-Purpose Hybrid ADCs
• Optical Character Recognition
• Radar Pulse Analysis
• Motion Signature Analysis
• P Data Acquisition SystemsPinout
SpecificationsDC Supply Voltage Range (VDD or VAA+) . . . . . . . . . . -0.5V to +8V
(Referenced to VSS or VAA- Terminal, Whichever is More Negative)
Input Voltage Range
CE2 and CE1 . . . . . . . . . . . . . . . . . . . .. . VAA- -0.5V to VDD + 0.5V
Clock, Phase, VREF -, 1/2 Ref . . . . . . . . . VAA- -0.5V to VAA+ + 0.5V
Clock, Phase, VREF -, 1/4 Ref . . . . . . . . . . VSS- -0.5V to VDD + 0.5V
VIN, 3/4 REF, VREF+ . . . . . . . . . . . . . . . . . .VAA- -0.5V to VAA- + 7.5V
Output Voltage Range, . . . . . . . . . . . . . . . VSS - 0.5V to VDD + 0.5V
Bits 1-8, Overflow (Outputs Off)
DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Clock, Phase, CE1, CE2, VIN, Bits 1-8, Overflow
DescriptionThe CA3318 is a CMOS parallel (FLASH) analog-to-digital converter designed for applications demanding both low power consumption and high speed digitization.
The CA3318 operates over a wide full scale input voltage range of 4V up to 7.5V with maximum power consumption depending upon the clock frequency selected. When operated from a 5V supply at a clock frequency of 15MHz, the typical power consumption of the CA3318 is 150mW. The intrinsic high conversion rate makes the CA3318 ideally suited for digitizing high speed signals. The overflow bit makes possible the connection of two or more CA3318s in series to increase the resolution of the conversion system. A series connection of two CA3318s may be used to produce a 9-bit high speed converter. Operation of two CA3318s in parallel doubles the conversion speed (i.e., increases the sampling rate from 15MHz to 30MHz).
256 paralleled auto balanced voltage comparators measure the input voltage with respect to a known reference to produce the parallel bit outputs in the CA3318.
255 comparators are required to quantize all input voltage levels in this 8-bit converter, and the additional comparator is required for the overflow bit.
CA3318 Data Sheet
