Features: The C8051F41x SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications.
An extended interrupt handler allows the numerous analog and digital peripherals to operate independently of the controller core and interrupt the controller only when necessary. By requiring less intervention from the microcontroller core, an interrupt-driven system is more efficient and allows for easier implementation of multi-tasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor, a Watchdog Timer, a Missing Clock Detector, a voltage level detection from Comparator0, a smaRTClock alarm or missing smaRTClock clock detector reset, a forced software reset, an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently enabled in software after a power-on reset during MCU initialization.
The internal oscillator is factory calibrated to 24.5 MHz ±2%. An external oscillator drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. A clock multiplier allows for operation at up to 50 MHz. The dedicated smaRTClock oscillator can be extremely useful in low power applications, allowing the system to maintain accurate time while the MCU is not powered, or its internal oscillator is suspended. The MCU can be reset or have its oscillator awakened using the smaRTClock alarm function.
Pinout
Specifications
| Parameter |
Min |
Max |
Units |
| Ambient temperature under bias |
-55 |
125 |
°C |
| Storage Temperature |
-65 |
150 |
°C |
| Voltage on VREGIN with respect to GND |
-0.3 |
5.5 |
V |
| Voltage on VDD with respect to GND |
-0.3 |
3.0 |
V |
| Voltage on VRTC-BACKUP with respect to GND |
-0.3 |
5.5 |
V |
| Voltage on XTAL1 with respect to GND |
-0.3 |
VDD+0.3 |
V |
| Voltage on XTAL3 with respect to GND |
-0.3 |
5.5 |
V |
Voltage on any Port I/O Pin (except Port 0 pins) or
RST with respect to GND |
-0.3 |
VIO+0.3 |
V |
| Voltage on any Port 0 Pin with respect to GND |
-0.3 |
5.5 |
V |
| Maximum output current sunk by any Port pin |
|
100 |
mA |
| Maximum output current sourced by any Port pin |
|
100 |
mA |
Maximum Total current through VDD, VIO,
VRTC-BACKUP, VREGIN, and GND |
|
500 |
mA |
*Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability
C8051F412 Data Sheet
