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C167CS-L16M3V

Features: • High Performance 16-bit CPU with 4-Stage Pipeline 125 ns Instruction Cycle Time at 16 MHz CPU Clock 625 ns Multiplication (16 * 16 bit), 1250 ns Division (32/16 bit) Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and Operating Systems Register...

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SeekIC No. : 004308054 Detail

C167CS-L16M3V: Features: • High Performance 16-bit CPU with 4-Stage Pipeline 125 ns Instruction Cycle Time at 16 MHz CPU Clock 625 ns Multiplication (16 * 16 bit), 1250 ns Division (32/16 bit) Enhanced Boole...

C167CS-L16M3V Data Sheet

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Part Number:
C167CS-L16M3V
Supply Ability:
5000

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Product Details

Description



Features:

• High Performance 16-bit CPU with 4-Stage Pipeline
125 ns Instruction Cycle Time at 16 MHz CPU Clock
625 ns Multiplication (16 * 16 bit), 1250 ns Division (32/16 bit)
Enhanced Boolean Bit Manipulation Facilities
Additional Instructions to Support HLL and Operating Systems
Register-Based Design with Multiple Variable Register Banks
Single-Cycle Context Switching Support
16 MBytes Total Linear Address Space for Code and Data
1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 62 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input
• On-Chip Memory Modules
3 KBytes On-Chip Internal RAM (IRAM)
8 KBytes On-Chip Extension RAM (XRAM)
• On-Chip Peripheral Modules
24-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 s
Two 16-Channel Capture/Compare Units
4-Channel PWM Unit
Two Multi-Functional General Purpose Timer Units with 5 Timers
Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
Two On-Chip CAN Interfaces (Rev. 2.0B active) with 2 * 15 Message Objects (Full CAN/Basic CAN), can work on one bus with 30 objects
On-Chip Real Time Clock
• Up to 16 MBytes External Address Space for Code and Data
Programmable External Bus Characteristics for Different Address Ranges
Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width
Five Programmable Chip-Select Signals
Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 144-Pin MQFP Package


Pinout

Connection Diagram


Specifications

Parameter
Symbol
Limit Values
Unit
Notes
min.
max.
Storage temperature
TST
-65
150
°C
-
Junction temperature
TJ
-40
150
°C
under bias
Voltage on VDD pins with
respect to ground (VSS)
VDD
-0.5
6.5
V
-
Voltage on any pin with
respect to ground (VSS)
VIN
-05
VDD + 0.5
V
-
Input current on any pin
during overload condition
-
-10
10
mA
-
Absolute sum of all input
currents during overload
condition
-
-
|100|
mA
-
Power dissipation
PDISS
-
1.5
W
-

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.




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